Design and Implementation of a Scalable High-Performance AES Cipher Chip
碩士 === 輔仁大學 === 電子工程學系 === 93 === A scalable high-performance AES cipher processor is proposed in this thesis. Since the design and implementation of the S-Box is the critical step for implementing the entire AES encipher/decipher, a modularized methodology is adopted to implement it. According to t...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2004
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| Online Access: | http://ndltd.ncl.edu.tw/handle/hqh7g6 |