A Verification Platform for SoC Bus Interface
碩士 === 逢甲大學 === 資訊工程所 === 93 === The advance of the system-on-chip（SoC）design paradigms makes the verification of bus interface protocol compliance increasingly important to the success of a SoC project. In this thesis, a verification platform is established by using visual Tcl/Tk in the Linux envi...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2005
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| Online Access: | http://ndltd.ncl.edu.tw/handle/77614467451680372340 |