The Design and Implementation of Built-In Scan Delay Measurement Cell
碩士 === 大葉大學 === 電機工程學系碩士班 === 93 === The accurate delay measurement is a major issue to test advanced SoC chips. The low/noisy supply voltage induces CUT delay, and makes the SCAN testing technique hard to capture the correct output delay responses. In this thesis, we propose a built-in delay testin...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2005
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| Online Access: | http://ndltd.ncl.edu.tw/handle/74272973137540384704 |