The impact of poly gate sidewall oxide thickness on MOSFET’s gate-induced drain leakage behavior

• Main Authors: Huang Tao Kun, 黃道坤
• Other Authors: J.P.Lin
• Format: Others
• Language: zh-TW
• Published: 2005
• Online Access: http://ndltd.ncl.edu.tw/handle/12981841264445016012

碩士 === 長庚大學 === 電子工程研究所 === 93 === The leakage in the drain region is a crucial issue for scaling of the MOSFET. The off-state gate-induced drain leakage (GIDL) current is one of the major contributors to the overall MOSFET leakage. GIDL is induced by band-to-band tunneling (BTBT) effect in the depletion region and generated in the gate to drain overlap region with high electric field. GIDL leakage is a function of many process parameters such as spacer material, spacer width, gate oxide thickness, doped concentration; anneal temperature, and poly re-oxidation conditions etc. Devices used in this work consist of a gate oxide of 4nm or 6nm, and a spacer width of 25nm. Three different poly re-oxidation conditions result in 3 gate sidewall oxide thicknesses of 4nm, 6nm, and 8nm, measured on the shallow trench isolation processed wafers in the experiments. The impact of different gate sidewall oxide thicknesses (4nm, 6nm and 8nm) on device threshold voltage (Vt), overlap capacitance (Cgd), and off-state GIDL leakage current was investigated. This study shows that the use of thin sidewall oxidation thickness further increases GIDL leakage current, getting high overlap capacitance, and decrease threshold voltage (Vt). Finally, a comparison of GIDL behavior in n-poly gate surface-channel NMOS and n-poly gate buried channel PMOS is summarized.