Effects of Dopant Out-Diffusion Deposited Different Poly-Si Thickness and Temperature for Buried Strap of DRAM Technology
碩士 === 長庚大學 === 電子工程研究所 === 93 === In DRAM process, a deep trench’s 2nd poly-Si & 3rd poly-Si play the key roles as buried strap forming supplier. As impurity in poly-Si crystal went through intrinic poly-Si and nitride interface diffusing into silicon subsrate. The various poly-Si process cause...
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| Format: | Others |
| Language: | en_US |
| Published: |
2005
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| Online Access: | http://ndltd.ncl.edu.tw/handle/10183557199169007376 |
| Summary: | 碩士 === 長庚大學 === 電子工程研究所 === 93 === In DRAM process, a deep trench’s 2nd poly-Si & 3rd poly-Si play the key roles as buried strap forming supplier. As impurity in poly-Si crystal went through intrinic poly-Si and nitride interface diffusing into silicon subsrate. The various poly-Si process cause different impurity mobility and solid solubility, it also affect the concentration of As in buried strap region and directly control burid strap contact resistance.
The stability of contact resistance of buried strap is a significant index to make a healthy array device of DRAM(Dynamic Ramdom Access Memory). Higher contact resistance will cause the charge sharing fail due to RC delay from deep trench capacitor to bit line in DRAM operation. Lower contact resistance will also cause sub-threshold leakage from nMOSFET device due to As over-diffusing to nMOSFET channel.
In this thesis, I study the character of As doped poly-Si to provide a clear mechanism to help us well known the relationships between poly-Si and nMOSFET device to overcome the challenge from deep sub micron generation of DRAM process.
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