Clock Skew Scheduling and Optimization for Large-Scale Digital Synchronous Circuits
碩士 === 長庚大學 === 電機工程研究所 === 93 === This thesis will study the problem of an optimal clock skew scheduling for large-scale synchronous VLSI circuits. In the problem formulation phase, we formulate the clock skew scheduling problem as a constrained quadratic programming (QP) problem. From a reliabilit...
| Main Authors: | , |
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2005
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| Online Access: | http://ndltd.ncl.edu.tw/handle/31862676760789643015 |