Design of 0.18-µm CMOS 2-/5-GHz Voltage-Controlled Oscillators and Single-Chip Phase-Locked Loop
碩士 === 國立中正大學 === 電機工程研究所 === 93 === This thesis presents the design, implementation,and measurement of two chips, which are a 2-GHz CMOS mixed-signal Phase locked-loop, and a 5-GHz CMOS quadrature VCO. The PLL and quadrature VCO were fabricated with the 0.18µm CMOS technology, both were mounted on...
| Main Authors: | , |
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2005
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| Online Access: | http://ndltd.ncl.edu.tw/handle/54657159503289473790 |