AREA-EFFICIENT FPGA IMPLEMENTATION OF RADIX-4 PIPELINED FAST FOURIER TRANSFORM PROCESSOR
碩士 === 大同大學 === 通訊工程研究所 === 92 === This paper introduces several algorithms and compares the computational complexity first. Second, we introduce two FFT (Fast Fourier Transform) architectures and it includes of pipelined based architecture and memory based architecture. Because we cost a lot of are...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2004
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| Online Access: | http://ndltd.ncl.edu.tw/handle/83088169435048312325 |
| Summary: | 碩士 === 大同大學 === 通訊工程研究所 === 92 === This paper introduces several algorithms and compares the computational complexity first. Second, we introduce two FFT (Fast Fourier Transform) architectures and it includes of pipelined based architecture and memory based architecture. Because we cost a lot of area size in multiplication, we reduce the multiplication in each stage. And then we use the CORDIC (Coordinate Rotation Digital Computer) operator to reduce the computation of twiddle factor. Finally, we propose a new architecture to minimize the area size and implement it in FPGA.
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