DESIGN OF A 5.8-GHz CMOS
碩士 === 大同大學 === 電機工程研究所 === 92 === This thesis designs a 5.8-GHz PLL based frequency synthesizer for wireless commutation system. The frequency synthesizer consists of a phase-frequency detector, a charge pump, a loop filter, a LC-tank VCO and a pulse-swallow architecture frequency divider with ouly...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2004
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| Online Access: | http://ndltd.ncl.edu.tw/handle/34985462612026108016 |
| Summary: | 碩士 === 大同大學 === 電機工程研究所 === 92 === This thesis designs a 5.8-GHz PLL based frequency synthesizer for wireless commutation system. The frequency synthesizer consists of a phase-frequency detector, a charge pump, a loop filter, a LC-tank VCO and a pulse-swallow architecture frequency divider with ouly one counter.
The proposed LC-tank voltage-controlled oscillator adopts double cross-coupled pair in order to get larger output voltage swing and low phase noise. The new dual-modulus prescaler can decrease power consumption and reduce chip area. By regulating the appropriate value of the propose pulse-swallow divider, it can change four difference channels.
The frequency synthesizer is designed by TSMC 0.18-µm single poly, six-metal CMOS process. The ADS simulation results justify the feasibility of our proposed frequency synthesizer.
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