DESIGN OF A 5.8-GHz CMOS
碩士 === 大同大學 === 電機工程研究所 === 92 === This thesis designs a 5.8-GHz PLL based frequency synthesizer for wireless commutation system. The frequency synthesizer consists of a phase-frequency detector, a charge pump, a loop filter, a LC-tank VCO and a pulse-swallow architecture frequency divider with ouly...
| Main Authors: | , |
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2004
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| Online Access: | http://ndltd.ncl.edu.tw/handle/34985462612026108016 |