The 1.8~1.6nm Gate Dielectrics Prepared by Plasma-Nitridation for 0.13um CMOS Technology Application and Beyond

碩士 === 國立臺北科技大學 === 機電整合研究所 === 92 === In order to improve the device performance, gate oxide has been scaled aggressively. The gate leakage current through the gate oxide increases significantly because direct tunneling is the primary conduction mechanism. The high gate leakage increases...

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Main Authors: Pan, Chun-Peng, 潘俊澎
Other Authors: Huang, Heng-Sheng
Format: Others
Language:en_US
Published: 2004
Online Access:http://ndltd.ncl.edu.tw/handle/48938724714296935755
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spelling ndltd-TW-092TIT006510422016-06-15T04:17:51Z http://ndltd.ncl.edu.tw/handle/48938724714296935755 The 1.8~1.6nm Gate Dielectrics Prepared by Plasma-Nitridation for 0.13um CMOS Technology Application and Beyond 以電漿氮化法製造之1.8~1.6nm閘極介電層應用於0.13微米與先進製程之互補式金氧半電晶體 Pan, Chun-Peng 潘俊澎 碩士 國立臺北科技大學 機電整合研究所 92 In order to improve the device performance, gate oxide has been scaled aggressively. The gate leakage current through the gate oxide increases significantly because direct tunneling is the primary conduction mechanism. The high gate leakage increases standby power consumption, which is a major concern for low power device applications. Decoupled plasma nitridation of is a new technology using inductive coupling to generate nitrogen plasma and implant a high level of nitrogen concentration onto the top surface layer of an ultra-thin gate oxide. This will help to increase the dielectric constant of the gate dielectric, and improve the boron penetration problem in p-channel MOSFETs. Traditional nitrided oxide prepared using N2O or NO thermal nitridation will have nitrogen piling up at the oxide/substrate interface, which results in boron pile up within the oxide causing an increase in the electron trapping and degradation of the oxide reliability. In our study, using traditional nitrided oxide methods result in poor performance、worse resistance to boron penetration、small EOT (effective oxide thickness) decreasing range. In this thesis, we use the current-voltage (I-V) measurements, capacitance-voltage (C-V) measurements, and lots of electric parameters studies were used to characterize the MOSFETs performance with Decoupled-Plasma nitrided oxide and compared with conventional methods. Huang, Heng-Sheng 黃恆盛 2004 學位論文 ; thesis 63 en_US
collection NDLTD
language en_US
format Others
sources NDLTD
description 碩士 === 國立臺北科技大學 === 機電整合研究所 === 92 === In order to improve the device performance, gate oxide has been scaled aggressively. The gate leakage current through the gate oxide increases significantly because direct tunneling is the primary conduction mechanism. The high gate leakage increases standby power consumption, which is a major concern for low power device applications. Decoupled plasma nitridation of is a new technology using inductive coupling to generate nitrogen plasma and implant a high level of nitrogen concentration onto the top surface layer of an ultra-thin gate oxide. This will help to increase the dielectric constant of the gate dielectric, and improve the boron penetration problem in p-channel MOSFETs. Traditional nitrided oxide prepared using N2O or NO thermal nitridation will have nitrogen piling up at the oxide/substrate interface, which results in boron pile up within the oxide causing an increase in the electron trapping and degradation of the oxide reliability. In our study, using traditional nitrided oxide methods result in poor performance、worse resistance to boron penetration、small EOT (effective oxide thickness) decreasing range. In this thesis, we use the current-voltage (I-V) measurements, capacitance-voltage (C-V) measurements, and lots of electric parameters studies were used to characterize the MOSFETs performance with Decoupled-Plasma nitrided oxide and compared with conventional methods.
author2 Huang, Heng-Sheng
author_facet Huang, Heng-Sheng
Pan, Chun-Peng
潘俊澎
author Pan, Chun-Peng
潘俊澎
spellingShingle Pan, Chun-Peng
潘俊澎
The 1.8~1.6nm Gate Dielectrics Prepared by Plasma-Nitridation for 0.13um CMOS Technology Application and Beyond
author_sort Pan, Chun-Peng
title The 1.8~1.6nm Gate Dielectrics Prepared by Plasma-Nitridation for 0.13um CMOS Technology Application and Beyond
title_short The 1.8~1.6nm Gate Dielectrics Prepared by Plasma-Nitridation for 0.13um CMOS Technology Application and Beyond
title_full The 1.8~1.6nm Gate Dielectrics Prepared by Plasma-Nitridation for 0.13um CMOS Technology Application and Beyond
title_fullStr The 1.8~1.6nm Gate Dielectrics Prepared by Plasma-Nitridation for 0.13um CMOS Technology Application and Beyond
title_full_unstemmed The 1.8~1.6nm Gate Dielectrics Prepared by Plasma-Nitridation for 0.13um CMOS Technology Application and Beyond
title_sort 1.8~1.6nm gate dielectrics prepared by plasma-nitridation for 0.13um cmos technology application and beyond
publishDate 2004
url http://ndltd.ncl.edu.tw/handle/48938724714296935755
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