24-bit Automatic Verilog Code Generation of A General Audio Codec Processor Design
碩士 === 南台科技大學 === 電子工程系 === 92 === This thesis is to design a 24-bit audio processor using automatic verilog code generation method. The processor is based on RISC architecture to get better performance for audio compression and decompression. Three algorithms: G.711(A-Law , u-Law)、ADPCM and MELP(Mi...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2004
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| Online Access: | http://ndltd.ncl.edu.tw/handle/99960551877271132895 |