Analysis and Design of CMOS PWCL/DLL and PLL

• Main Authors: Sung-Rung Han, 韓松融
• Other Authors: Shen-Iuan Liu
• Format: Others
• Language: en_US
• Published: 2004
• Online Access: http://ndltd.ncl.edu.tw/handle/40301951075445192192

博士 === 國立臺灣大學 === 電機工程學研究所 === 92 === As the technology continuously scaling down, the short channel effects and the presence of the voltage, process, and temperature variations make the circuit hard to design. For solving these problems, the feedback technique is widely used. To acquire the clock phase and to assure the duty cycle of the clock, it results in the growth of the phase-locked loops (PLLs), delay-locked loops (DLLs), and pulsewidth control loops (PWCLs). This thesis mainly dedicates to the analysis and improvement in these three fields. In this thesis, a PWCL, a PWCL with DLL, and a PLL were explored and fabricated in the 0.35μm process. First, a fast-locking PWCL with its circuit models and mathematical analysis are proposed. The circuit models of the PWCL are derived first. Based on the circuit models, the lock times corresponded to the conventional and the proposed PWCLs can be calculated. The experimental results verify the analysis and achieve fast-locking capability. Second, a new single-path PWCL with built-in DLL is presented. This PWCL can cooperate with a DLL and the voltage-controlled delay line (VCDL) in a DLL can be integrated with the buffer line in a PWCL. The trade-off between the duty cycle precision and the robustness against the process and temperature variations can be eliminated. Also, the tuning range of the duty cycle can theoretically be extended to 100% duty cycle. Moreover, the duty cycle of the output clock is presettable. Finally, the research concentrates on a PLL. The objects of this chapter have two parts: time constant calibration in the loop filter and fast-locking design. Based on the time constant calibration, the loop dynamics, damping factor and natural frequency, can track with the period of the reference clock. In the fast-locking design, two methods are proposed to reduce the lock times in the frequency and phase acquisitions. To compare the lock times spent in the conventional and the proposed PLL mathematically, a method to estimate the lock time in a PLL with the cycle-slipping phenomenon is derived.