| Summary: | 碩士 === 國立清華大學 === 電機工程學系 === 92 === RT-level power estimation is to quickly predict the total switching activity in a logic design without resorting to the time-consuming gate-level simulation. This thesis investigates an RTL power estimation methodology suitable for large designs. In order to retain high accuracy, a number of features are proposed, including a power mode classification method and a functional-weighting scheme for linear approximation. Furthermore, in order to take into account the temporal and spatial correlations among the input patterns, we use a cycle-by-cycle modeling scheme. On top of it, each primary input is further encoded into two binary variables to faithfully reflect its switching behavior. The proposed method has been realized as a practical tool that can fit into the commercial design flow and tested by a number of real designs. Experimental results show that the average estimation error as compared to full gate-level simulation is only 3.82%.
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