RTL Power Estimation Using Power Mode Classification and Functional Weighting
碩士 === 國立清華大學 === 電機工程學系 === 92 === RT-level power estimation is to quickly predict the total switching activity in a logic design without resorting to the time-consuming gate-level simulation. This thesis investigates an RTL power estimation methodology suitable for large designs. In order to retai...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2004
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| Online Access: | http://ndltd.ncl.edu.tw/handle/94553458737160847384 |