The Worst-Case Accumulated Jitter Measurement for Phase-Locked Loops
碩士 === 國立清華大學 === 電機工程學系 === 92 === This paper presents a Time-to-Digital Converter (TDC) circuit to measure the worst-case accumulated jitters over N periods of the PLL output signal. The worst-case jitters that include the most positive jitter and the most negative jitter can be calculated through...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2004
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| Online Access: | http://ndltd.ncl.edu.tw/handle/26208716863399403809 |