| Summary: | 博士 === 國立清華大學 === 電機工程學系 === 92 === The objective of this dissertation is to explore in depth the feasibility of continued scaling for the nanoscale MOSFET devices through precise modeling of short-channel effect and proper design of channel profile and device structure. The analytical short-channel effect models without any fitting parameter have been successfully derived for nanoscale MOSFETs from analytical solutions of 2D Poisson''s equation, including the sophisticated device structures such as ultra-shallow and graded source/drain junctions, and nonuniform retrograde and halo-doped channels. Detailed investigations and comparisons on short-channel effect are performed for wide ranges of device dimensions and technologies along with 2D numerical device simulations. The design considerations of channel profile and device structure are investigated for the optimization of short-channel effect and drain leakage current for nanoscale MOSFET devices. By using fully CMOS-compatible process, a novel Insulated Shallow Extension (ISE) is proposed for achieving sub-50 nm bulk MOSFETs. A design strategy of channel profile by using localized halo is also proposed for this new ISE structure. By combining this ISE structure with localized halo, sub-50 nm bulk MOSFET devices can be easily achieved with small threshold voltage roll-off, low drain leakage current, and suitable threshold voltage level.
The short-channel effect models for nanoscale MOSFETs have been derived by using the effective-doping model. By viewing the MOSFET as distributed MOS capacitors in series, the short-channel threshold voltage is simply equal to the highest threshold voltage among them, that is the one with the highest distributed effective-doping concentration. The effective-doping model has the advantage of its capability in retaining the physical insight of the short-channel effect and incorporating 2D analytical solutions of Poisson''s equation. The scale-length approach for solving 2D Poisson''s equation is successfully extended to find the channel potential of MOSFET with nonuniform channels and various junction profiles. Based on the superposition principle and variable-separation method, this scale-length solution can give an excellent representation of the channel potential in the neighborhood of maximum potential barrier. Excellent agreements between the numerical simulated results and these short-channel effect models have been obtained for wide ranges of device dimensions and technologies. This model can lead to better understanding of the scaling limits and the impact of various device parameters on the short-channel effect. Since no empirical fitting parameters are involved in the derivations, it should be very helpful for the analysis and design of next generation bulk CMOS devices.
The sophisticated design considerations of channel profile and device structure are one of the key challenges in developing the state-of-the-art nanoscale technology. The design strategy of channel profile is very important for achieving the sub-50 nm bulk CMOS devices. With the optimal choice of the location of heavy doped halo, it can be simultaneously accomplished to improve the roll-off of threshold voltage and to relieve drain band-to-band leakage current without raising the low threshold voltage. The adequate halo-to-extension spacing is the most effective design parameter to control the band-to-band leakage current and the threshold voltage roll-off. Instead of P-N junction, a sidewall dielectric oxide of proposed ISE structure is used to define the shallow extension to provide the precise control of the halo-to-extension spacing to achieve a sub-50 nm bulk MOSFET successfully. The combination of ISE with localized halo results in excellent short-channel behavior. It shows excellent performance on the short-channel behavior over the conventional bulk devices and serves a promising alternative of bulk MOSFET in sub-50 nm regime.
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