A 3.3V 10-bit 50-MS/s Pipelined Analog-to-Digital Converter with Low-Deviation MDAC
碩士 === 國立中山大學 === 電機工程學系研究所 === 92 === A 10-bit 50MSample/sec pipelined analog-to-digital converter is described in this thesis. We replaced conventional multiplying digital-to-analog converter with low-deviation multiplying digital-to-analog converter in the proposed pipelined analog-to-digital co...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2004
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| Online Access: | http://ndltd.ncl.edu.tw/handle/81125939091064318069 |
| Summary: | 碩士 === 國立中山大學 === 電機工程學系研究所 === 92 === A 10-bit 50MSample/sec pipelined analog-to-digital converter is described in this thesis. We replaced conventional multiplying digital-to-analog converter with low-deviation multiplying digital-to-analog converter in the proposed pipelined analog-to-digital converter. Using nonregular feedback capacitors achieves better linearity than using conventional regular feedback capacitors in the multiplying digital-to-analog converter. The accuracy of this pipelined analog-to-digital converter can be also improved, the result shows that the DNL is ±0.31 LSB, INL is about ±0.57LSB.
Our proposed pipelined analog-to-digital converter is designed by TSMC 2P4M 0.35um process. It operates at 3.3V power supply voltage with 0.5 to 2.5V reference voltage, and the power consumption is about 64mW.
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