A 3.3V 10-bit 50-MS/s Pipelined Analog-to-Digital Converter with Low-Deviation MDAC
碩士 === 國立中山大學 === 電機工程學系研究所 === 92 === A 10-bit 50MSample/sec pipelined analog-to-digital converter is described in this thesis. We replaced conventional multiplying digital-to-analog converter with low-deviation multiplying digital-to-analog converter in the proposed pipelined analog-to-digital co...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2004
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| Online Access: | http://ndltd.ncl.edu.tw/handle/81125939091064318069 |