| Summary: | 碩士 === 國立中山大學 === 電機工程學系研究所 === 92 === Small size of electronic product with high layout density is the future trend in today’s high speed digital circuit design. A circuit designer is obliged to optimize the best solution of circuit layout in a limited area in order to both keep a good signal integrity（SI）, and save the layout space. Meander delay line is one of the challenging topic in high-speed circuit. In this dissertation, a effective method is provided to design a meander delay line, and FDTD and HFSS are matched up to predict the behavior and the character of the meander delay line; the differential meander delay line is compared with the single meander delay line, and the behavior and phenomena of the differential meander delay line are discussed. To reduce couple power, the differential meander line of design would be a new thinking. The most important point in this thesis, the complete flows of designing single meander lines and differential meander lines are provided, and designer could follow the steps of the proposed method to design a perfect and practical meander line with both keeping good SI and using least layout space. The effect of the design parameters of the meander line on the signal quality both in time-domain and frequency-domain is theoretically and experimentally investigated. FDTD method and the commercial tool HFSS are employed for the numerical study in this work.
|
|---|
