The Design and Analysis of a Meander Delay Line in a High Speed Digital System
碩士 === 國立中山大學 === 電機工程學系研究所 === 92 === Small size of electronic product with high layout density is the future trend in today’s high speed digital circuit design. A circuit designer is obliged to optimize the best solution of circuit layout in a limited area in order to both keep a good signal integ...
| Main Authors: | , |
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| Format: | Others |
| Language: | zh-TW |
| Online Access: | http://ndltd.ncl.edu.tw/handle/hza8zx |