Software Design of An Axiom-Based Equivalence Verification Method
碩士 === 國立中山大學 === 電機工程學系研究所 === 92 === High-level finite-state-machine is a behavioral level hardware system design specification method. Each of its state transitions is tagged with a description of an expression executed during the corresponding state transition. In order to verify the equivalence...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2004
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| Online Access: | http://ndltd.ncl.edu.tw/handle/83431885338841563101 |