Design and Implementaion of a High-Performance Memory Generator
碩士 === 國立中山大學 === 資訊工程學系研究所 === 92 === The SRAM memory generator in this thesis is divided into four parts: row decoder, storage cell, column decoder, and sense amplifier & write controller. The row decoder is designed using pass-transistors logic with better area and regularity compared with co...
| Main Authors: | , |
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| Format: | Others |
| Language: | en_US |
| Published: |
2004
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| Online Access: | http://ndltd.ncl.edu.tw/handle/97509351527568588040 |