Built-in Self-test Circuits for Pipeline Analog-to-Digital Converters
碩士 === 國立交通大學 === 電機與控制工程系所 === 92 === In this thesis, our target is to design a built-in self-test circuit for the pipeline analog-to-digital converters. We propose a new approach. According to the probability of each stage sample-and-hold output signals, we can test the voltage offset error of eac...
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| Format: | Others |
| Language: | en_US |
| Published: |
2004
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| Online Access: | http://ndltd.ncl.edu.tw/handle/7s8222 |