Low Leakage Charge Pumping Measurement Techniques for Advanced CMOS with Gate Oxide in the 1nm Range

• Main Authors: Feng Hsin Jung, 馮信榮
• Other Authors: Steve S. Chung
• Format: Others
• Language: en_US
• Published: 2004
• Online Access: http://ndltd.ncl.edu.tw/handle/t6y85p

碩士 === 國立交通大學 === 電子工程系所 === 92 === As device scaling continues, the sub-100nm CMOS device needs a gate oxide thickness in the range of 10-15Å and with 75nm gate length in 2005, as predicted from the SIA roadmap. How to monitor oxide quality for ultra-thin gate oxide with tunneling leakage current is crucial for the next generation CMOS technology, in particular the monitoring of interface traps (Nit) and oxide trapped charges (Qot) in the gate oxide. So far, various gate oxide reliability diagnostic tools, such as DCIV, GD(Gated-Diode), CP(Charge-Pumping) etc. have been employed for such a purpose. For ultra-thin gate oxide down to below 20 Å, the above methods are limited by the tunneling leakage through the gate oxide during the measurement since direct tunneling exists. This thesis has been focused on developing new techniques for the measurement of ultra-thin gate oxide 90nm CMOS devices. We have successfully developed new method, combing IFCP method to remove direct tunneling current and an improved three-steps neutralization to separate Nit and Qot measurement technique. The test sample in this work is prepared based on the DPN gate oxide process. The EOT of gate oxide thickness are 14Å and 16 Å, which have three different nitrogen concentrations, respectively. We compare the oxide thickness dependence and concentration of plasma nitridation of CMOS device under HC stress and NBTI stress from the lateral profiling of interface traps and oxide traps. In short channel length, the dominate stress condition of device degradation switched from IB,max to VG= VD. Under VG= VD stress condition, the gate oxide with higher plasma nitrogen density and thinner thickness has better reliability for nMOSFET and the gate oxide with lower plasma nitrogen density and thicker thickness has better reliability for pMOSFET. Moreover, we found that nitrogen played an important role in device reliability under NBTI stress. From the result of the distribution for interface traps, we know that the highest nitrogen in oxide has worst case device degradation under NBTI stress for pMOSFET. In addition, we have seen that NBTI-like stress enhances HC effect at high temperature and the lowest nitrogen content has the best reliability in pMOSFET.