Low Leakage Charge Pumping Measurement Techniques for Advanced CMOS with Gate Oxide in the 1nm Range
碩士 === 國立交通大學 === 電子工程系所 === 92 === As device scaling continues, the sub-100nm CMOS device needs a gate oxide thickness in the range of 10-15Å and with 75nm gate length in 2005, as predicted from the SIA roadmap. How to monitor oxide quality for ultra-thin gate oxide with tunneling leakage current i...
| Main Authors: | , |
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| Format: | Others |
| Language: | en_US |
| Published: |
2004
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| Online Access: | http://ndltd.ncl.edu.tw/handle/t6y85p |