An Application of TOC for Lot Releasing and Dispatching Model under Stepper Group Limitation
碩士 === 國立交通大學 === 管理學院碩士在職專班工業工程與管理組 === 92 === From micron to nanometer technology in semiconductor manufacturing, increasing investment capital and more precise lithography in high-density device is the tendency and challenge to IC (Integrated Circuit) function enhancement and cost reduction. Obvi...
| Main Authors: | , |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2004
|
| Online Access: | http://ndltd.ncl.edu.tw/handle/33603990525889196200 |