A Study of the Fabrication of Flip-Chip Bumps Using Dry-film Photoresist Process on 300mm wafer

• Main Authors: Keng-Huei Shen, 沈庚輝
• Other Authors: Edward Y.Chang
• Format: Others
• Language: zh-TW
• Published: 2004
• Online Access: http://ndltd.ncl.edu.tw/handle/87486195800216197288

碩士 === 國立交通大學 === 產業安全與防災學程碩士班 === 92 === This work is to study the dry-film photoresist to form patterns for Flip-Chip bumps on 300 mm wafers. The so-called “double-deck metal seed layer” process was also applied in this study by using sputtered 1000 Å Ti (Titanium) and 5000 Å Cu (Copper) metal layers. By welding the metal and solder electroplating technology on the chip of the integrated circuits (ICs), Cu / Ni(nickel) / Solder alloy fill up hole under bumps metallization (UBM) after solder re-flowing at 220oC. A very high yield performance is achieved. This technology has the advantages of low production cost of manufacturing Flip-Chip Bumps on 300mm wafer. This research optimizes the parameters of the dry-film photoresist, lithography technology, metal sputtering technology and metal electroplating technology, and etc. Meanwhile, the final dimension of the solder structure is verified in order to minimize the minimum the manufacturing cost and increased the yield. The lithography technology has been applied to the IC package and printed circuit board(PCB). Small critical dimension (CD) on a large wafer is a important process in the future. In this study, the dry-film photoresist (thickness is 120μm, surface uniformity < 1.5%) soft bake at 70oC is used to solve this problem. The position of solder bumps is defined by photo lithography technology. Using temperature of 140 oC and electroplating Ni 10 min. Ni metal layer with thickness of 3.5μm is a good diffusion barrier for Pb-Sn eutectic solder. The thickness of the Pb-Sn metal compound is increased with the process time of the electroplating. As a result, a high-yield and low-cost technology is obtained for mass-production of Flip-Chip bumps.