A 6-bit 1-Gsample/sec Analog-to-Digital Converter
碩士 === 國立成功大學 === 電機工程學系碩博士班 === 92 === This thesis proposes a 6-b 1G-sample/sec A/D Converter. The converter is suitable to optical (magnetic) read-channel and high-speed Ethernet chips. The flash structure is adopted to accomplish the requirement of higher speed. Moreover, system performance is...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2004
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| Online Access: | http://ndltd.ncl.edu.tw/handle/68256508837993563560 |
| Summary: | 碩士 === 國立成功大學 === 電機工程學系碩博士班 === 92 === This thesis proposes a 6-b 1G-sample/sec A/D Converter. The converter is suitable to optical (magnetic) read-channel and high-speed Ethernet chips. The flash structure is adopted to accomplish the requirement of higher speed. Moreover, system performance is increased by using fully differential methods. These include an on-chip T/H to eliminate the sampling time skews resulted from the fact that the clock and input signal are being transmitted to numerous comparators, and further enhance the dynamic performance. In additional, there are elaborated considerations made for enabling digital encoders to be operating stably in high speed.
The chip area is 1.2x1.2mm2 in TSMC 0.18μm CMOS 1P6M mixed-signal process. Simulation results show that the converter can achieve effective number of bit higher than 5.2 at the input frequency up to 496MHz and sampling frequency up to 1-Gsample/sec. The converter consumes 180mW at 1.8V when operating at 1-Gsample/sec.
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