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碩士 === 國立成功大學 === 材料科學及工程學系碩博士班 === 92 === The application of the semiconductor devices were seriously effected by the dielectric property between coating layers and the metal-conduct-line. Interconnect delay is a factor of performance limiting for ULSI circuits when feature size is scaled to deep...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2004
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| Online Access: | http://ndltd.ncl.edu.tw/handle/12016442826208885769 |