| Summary: | 碩士 === 國立中興大學 === 電機工程學系 === 92 === Abstract
A memory cell storing more than one bit per cell is termed multilevel memory. Several techniques to implement multilevel flash cells have been proposed. The first category consists of controlling the amounts of charge stored in the single floating gate for multilevel operation, but the peripheral circuit becomes more complicated. The second category consists of the store charges in different locations of a flash cell. We design an asymmetrical split floating gate (ASFG) of multilevel flash memory devices belonged to the second category. The structure of ASFG is like the split gate flash. The ASFG use FN tunneling method to store different amounts of the charge in different floating gates, and to generate different threshold voltage to achieve 4-level operation. It uses FN (tunneling mechanism) for programming and erasure operation in order to low power consumption. In addition, in the reading way, the data can be read from the same electrode. In another way, it does require different electrodes to identify different logic levels. Therefore, the access time of the data from the same electrodes is less. So, we design the structure of ASFG that is reading in the same electrode.
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