Analysis and Design of a Multiphase-Output Delay-Locked Loop
碩士 === 國立中興大學 === 電機工程學系 === 92 === In this thesis, a multiphase-output delay-locked loop (DLL) is presented. In the proposed multiphase-output DLL, the start-controlled phase/frequency detector (PFD) is used to provide precise multiphase-output without the locking problem. The PFD utilizes a new NA...
| Main Authors: | , |
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2004
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| Online Access: | http://ndltd.ncl.edu.tw/handle/23365515226977897823 |