The Study of Electrical Characteristic and Fault Model for SoC Package
碩士 === 義守大學 === 電子工程學系 === 92 === Along with the rise time of signals becomes faster and a trend of SoC(System on a Chip). The input/output pin count is increasing in a package, and required high density of trace line or gold wire. But it is difficult to evaluate the best process parameter of assemb...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2004
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| Online Access: | http://ndltd.ncl.edu.tw/handle/72985207050112062577 |