Clock-Tree Routing for System-on-a-Chip Design
碩士 === 義守大學 === 電子工程學系 === 92 === In this research, we propose a method combining the concepts of buffer-insertion with global-routing to build a zero-skew clock tree with less latency. First, we allocate a single buffer-block for buffer insertion in the chip. Perform global routing by...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2004
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| Online Access: | http://ndltd.ncl.edu.tw/handle/94732266278194534193 |