A Hardware Algorithm For Fast DigitOn-line Logarithmic Computation

• Main Authors: Hsueh-Chieh Chen, 陳學杰
• Other Authors: Chi-Chyang Chen
• Format: Others
• Language: zh-TW
• Published: 2004
• Online Access: http://ndltd.ncl.edu.tw/handle/16029346471174865672

碩士 === 逢甲大學 === 資訊工程所 === 92 === This propose of the paper is to combine a hardware algorithm for fast digit on-line logarithmic computation with a hardware algorithm for fast digit-parallel exponential computation. Combing with these two hardware algorithms, it will be the logarithmic number system (LNS) addition/subtraction unit. In this paper, we modified the multiplicative normalization and reduce it to several multipliers, adders with short bit length. As a result, we make it suitable for digit online computation and avoid the multiplication with long bit length simultaneously. The number of convergence stages in our logarithmic computation is only , where is the word length of the operand and , with being the radix chosen in the computation, but each convergence stage in our logarithmic computation need only needs several bits length of the operand. After each convergence stage we will get the partial precision of logarithmic computation. First, we use VHDL to design the hardware for 24-bit single precision on the FPGA as a test. ALTERA Company provides the NIOS development kits including simple OS and having the ability of communication and testing with personal computer. As a result, we realize the hardware as a co-processor by the development kits. Second, we design the hardware for 53-bit double precision as ASIC Chip, and the area is bigger than the original digit-parpllel algorithm only for one of the third.