A Hardware Algorithm For Fast DigitOn-line Logarithmic Computation
碩士 === 逢甲大學 === 資訊工程所 === 92 === This propose of the paper is to combine a hardware algorithm for fast digit on-line logarithmic computation with a hardware algorithm for fast digit-parallel exponential computation. Combing with these two hardware algorithms, it will be the logarithmic number system...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2004
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| Online Access: | http://ndltd.ncl.edu.tw/handle/16029346471174865672 |