Congestion-Driven Floorplan on DBL Representation
碩士 === 中華大學 === 資訊工程學系碩士班 === 92 === As VLSI technology reaches deep-sub micron dimensions and the application of SoC (System-on-Chip) design is general, the scale of VLSI circuit becomes more complex. A traditional area-driven floorplan become less import...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2004
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| Online Access: | http://ndltd.ncl.edu.tw/handle/31823566479877559331 |