Area-Driven Buffer Block Planning with Optimal Wire-Sizing Assignment

碩士 === 中華大學 === 資訊工程學系碩士班 === 92 === As VLSI circuits are scaled into advanced deep-submicron(DSM) dimensions, interconnection delay plays an important role for any performance-driven design. In general, the techniques of wire sizing and buffer insertion can be further used to reduce the...

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Bibliographic Details
Main Authors: Chao-Hung Lu, 呂昭宏
Other Authors: Jin-Tai Yan
Format: Others
Language:en_US
Published: 2004
Online Access:http://ndltd.ncl.edu.tw/handle/89251616633805816806