| Summary: | 碩士 === 長庚大學 === 電子工程研究所 === 92 === DRAM data retention time has nearly doubled for each generation due to the demand of high density for high speed and low power DRAMs. However, the electric field in memory cell is also becoming stronger and leakage current has been increasing with each generation resulting in poor retention characteristics. In the work, it was found that the back-end passivation films were skipped in the standard process flow of 0.14µm 256Mb DRAMs, the performance of the leakage current and the data retention time were significantly improved. Hence, the optimization of the passivation process was studied in detail.
It's well known that hydrogen penetration to the gate oxide interface is responsible for the degradation of the leakage current and the retention time. Our results also indicated that the minimization of hydrogen released from the passivation nitride is an effective way of improving the leakage current and the retention time. Another effective way is to deposit an oxide layer with higher density of dangling bonds under the passivation nitride. Interestingly, the increase of the passivation nitride thickness would not lead to a better leakage current and retention performance. A reasonable explanation is that only Si-H bonds at the interface of oxide and nitride diffuse to the gate oxide interface.
All experiments in this work were performed on ASM Eagle-10 PE CVD System. A three-stage DOE was applied to optimize the properties of passivation oxide and nitride films. And then, the key parameters of each film were identified for minimizing leakage current. A model to explain the leakage current and data retention degradation phenomenon was established successfully.
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