Design of the Architecture for Real Time Reconfigurable Digital IIR Filter
碩士 === 元智大學 === 電機工程學系 === 91 === The Architecture for Real time Reconfigurable Digital IIR Filter is proposed in thesis. It used SRAM (Static Random Access Memory) technology of FPGA (Field Programmable Gate Arrays) to achieve a Reconfigurable function and to build up a Co-processor syst...
| Main Authors: | , |
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2003
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| Online Access: | http://ndltd.ncl.edu.tw/handle/47299398120415975280 |