| Summary: | 碩士 === 大同大學 === 資訊工程研究所 === 91 === System-on-a-chip (SOC) design with IP (Intellectual Property) reuse becomes a key factor of IA design, and enables system or chip designer to increase the performance of the chip and decrease the time to market.
There are many mature synchronous design tools such as SYNOPSYS design compiler, CADENCE-opus, etc that are not suitable for SOC design. Some new tools such as SystemC and JHDL add software capability to specify both hardware and software in a single language, but they are not easy to design the plug-and playable reusable IP due to the clock integration problem between subsystems.
A CAD tool for SOC design, called SOCAD, and Hardware/Software co-design based on Java and self-timed systems technology is proposed. SOCAD provides the specification tool with Java programming language to describe system behaviors, translation tools to compile the Java programs into graph-based specifications represented by UML activity diagrams and to translate the graph-based specifications into VHDL codes automatically. This thesis focuses on the algorithms of compiling activity diagrams into self-timed systems in VHDL.
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