An Efficient Test Strategy for Fast Multiplier Core

• Main Authors: Chia-Hung Lin, 林家弘
• Other Authors: Jiann-Chi Rau
• Format: Others
• Language: zh-TW
• Published: 2003
• Online Access: http://ndltd.ncl.edu.tw/handle/67179265439370233252

碩士 === 淡江大學 === 電機工程學系 === 91 === To test core-based SoCs, an important step is to get test sets for testing cores. Soft cores are usually provided with hardware description languages such as VHDL and Verilog. It is much more difficult to generate test sets at higher level than at logic level. Tree structure summation in conjunction with Booth encoding are well known techniques to design fast multiplier cores widely used as embedded cores in the design of complex system on chip. From the viewpoint of core providers, the IP core designers not only employ design for testability (DFT) strategy for its cores, but also provide the most effective test sets for core users. In this paper, we propose a method to generate pseudo-exhaustive test patterns at function level. The proposed method can be used to generate test patterns for IP cores, especially, for soft IPs.