An Efficient Test Strategy for Fast Multiplier Core
碩士 === 淡江大學 === 電機工程學系 === 91 === To test core-based SoCs, an important step is to get test sets for testing cores. Soft cores are usually provided with hardware description languages such as VHDL and Verilog. It is much more difficult to generate test sets at higher level than at logic level. Tree...
| Main Authors: | , |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2003
|
| Online Access: | http://ndltd.ncl.edu.tw/handle/67179265439370233252 |