Low Overhead on RTL Orthogonal Scan Chain Design
碩士 === 國立臺北科技大學 === 電腦通訊與控制研究所 === 91 === As the IC (Integrated Circuit) industry continuously increases the number of transistors in a chip, the SOC (System on a chip) finally becomes a reality. At the same time, the testing cost of a chip increase well, so DFT (Design for Testability) features bec...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2003
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| Online Access: | http://ndltd.ncl.edu.tw/handle/01560850966328403031 |