20MHz 8-bit Sample-and-Hold Circuit with Double Sampling
碩士 === 國立清華大學 === 電子工程研究所 === 91 === This thesis describes a 20MHz, 8-bit resolution CMOS pseudodifferential sample-and-hold circuit with double sampling, which is to be mainly intended for front-end use in analog-to-digital converters. The circuit is composed of an operational amplifier,...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2003
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| Online Access: | http://ndltd.ncl.edu.tw/handle/51741590515153041092 |