Investigation on a New Embedded Flash Memory Cell Using a SPICE-compatible Hot Carrier Injection Model

• Main Authors: Shih-Chen, Wang, 王世辰
• Other Authors: Ya-chin, King
• Format: Others
• Language: en_US
• Published: 2003
• Online Access: http://ndltd.ncl.edu.tw/handle/71112768521637791024

碩士 === 國立清華大學 === 電子工程研究所 === 91 === A new embedded-flash-memory cell consisting of two transistors fabricated by a standard CMOS process has been proposed by our lab. The cell is verified with good program and erase characteristics, but further investigation are not completed yet. Owing to the full compatibility with the standard CMOS process, such investigations can be fulfilled by SPICE simulations. Though accurate device characteristics is already obtained by the BSIM device model, but the lack of a sub-circuit model of the gate current injection mechanisms prohibits further studies of the cell behavior. Hence, a simulation tool compatible with SPICE is built up for cell structure optimization. There are two major aims in this study. One is the built-up of the circuit element of hot-carrier injection and a sub-circuit model to simulate the proposed cell. Fairly good agreements between simulation results and the measurement data are obtained with our sub-circuit model. The second aim of this study is to investigate the effect of various cell parameters on the cell behavior. Three kinds of design parameters — cell dimensions, operating voltages, and process variations — are discussed in this work. The influences of design parameters are verified with physical intuitions, hand calculation and simulation results. Through such discussions, the design direction of the novel cell is revealed. Those conclusions therefore can help further improvement of the array structure and new program / erase schemes to obtain better cell performance.