Design of High Speed CMOS PLL for Multi-Frequency Band Application
碩士 === 國立東華大學 === 電機工程學系 === 91 === ABSTRACT In the modern mixed-signal integrated circuits and system on chip (SOC) environment design, phase locked loop (PLL) is the burning problem of designing consideration. However, one of the major issues in mixed analog and digital designs is the perfo...
| Main Authors: | , |
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2002
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| Online Access: | http://ndltd.ncl.edu.tw/handle/08594568991004506818 |