DESIGN OPTIMIZATION ON ESD PROTECTION CIRCUITS WITH GATE-COUPLED TECHNIQUE
碩士 === 國立交通大學 === 電資學院學程碩士班 === 91 === Gate-coupled technique has been used to lower device breakdown voltage and to ensure uniform ESD (ElectroStatic Discharge) current distribution in deep-submicron CMOS on-chip ESD protection circuit. But, the gate-coupled design has also been confirme...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2003
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| Online Access: | http://ndltd.ncl.edu.tw/handle/59768132531868343218 |