| Summary: | 碩士 === 國立交通大學 === 電子工程系 === 91 === In this study, the reliability of p-channel dynamic threshold voltage MOSFETs (DTMOS) is characterized. With increasing demands in high-speed and low-power digital electronics in recent years, DTMOS with its lower threshold voltage, higher transconductance, and enhanced current drive capability is very promising for future ULSI CMOS applications. However, the hot-carrier reliability data of p-channel DTMOS are still lacking, and this motivates us to carry out this work.
First, the characteristics of various gate structures including T-gate and H-gate were investigated. Since the presence of substrate contacts enables the efficient removal of charge in the body region, thus prevents carrier accumulations in the body region, and therefore reduces the impact ionization rate, devices with T-gate and H-gate exhibit better performance compared to the standard devices without substrate contacts.
Under DT-mode, by tying the gate to the body, the vertical electric field across the oxide is greatly reduced. So the probability of generated holes to surmount the Si/SiO2 energy barrier is greatly reduced. As a result, the threshold voltage shift is reduced. Since the effectiveness of the gate bias is amplified under DT-mode, a small change in charge trapping and/or interface trap generation would result in a large transconductance change during stress, compared to the normal mode operation. This results in worsen stress-induced transconductance degradation. The on-state current of DT-mode device exhibits enhanced degradation than the normal mode device due to the enhanced transconductance degradation.
Devices under DT-mode depict a larger temperature dependence on threshold voltage shift and transconductance degradation, decreasing and increasing more rapidly with the increasing and decreasing of temperature. It is also seen that devices stressed at higher temperature show less degradation. This is because impact ionization rate is decreased with increasing temperature. The effects of substrate doping concentration are also studied. It is found that for DT-mode, a higher substrate doping results in higher percentage change in device parameter. However, higher substrate doping concentration also increases the impact ionization rate, and aggravates stress-induced degradations under both normal and DT modes.
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