FABRICATION AND CHARACTERIZATION OF P-CHANNEL SHOCKTTY BARRIER POLY-SI THIN-FILM TRANSISTORS WITH PTSI SOURCE/DRAIN

• Main Authors: Wei Lee, 李維
• Other Authors: Tiao-Yuan Huang
• Format: Others
• Language: zh-TW
• Published: 2003
• Online Access: http://ndltd.ncl.edu.tw/handle/25610033292873026036

碩士 === 國立交通大學 === 電子工程系 === 91 === In this thesis, we have fabricated and characterized Shocktty barrier Poly-Si thin-film transistors (SBTFTs) with PtSi Source/Drain and field-induced drain (FID). The FID-SBTFT features an un-doped poly-Si channel layer with an offset channel region, a top field-plate (the sub-gate) lying over the passivation oxide and overlapping the entire offset channel region, and Pt-Silicided source/drain. In this work, the poly-Si channel layers were prepared by solid-phase crystallization (SPC) technique. It is worth mentioning that the performance in P-channel operation is much better than N-channel operation, with higher on/off current ratio and sharper subthreshold swing (SS). As a result, the device with PtSi is extremely promising for P-channel operation. In this thesis, we describe the importance of the SBTFTs with PtSi S/D on P-channel operation. In addition, Poly-Si TFTs featuring PtSi Source/Drain, and nano-scale channel Fin structure with 90nm channel length and 50nm width were fabricated and characterized. The use of nano-scale poly-Si channels allows stronger control of the channel potential by the gate bias, and therefore better subthreshold characteristics could be obtained. We compared the p-type performance of devices with two kinds of structures, and also studied the effects of sub-gate bias, main-channel length, and channel offset length. Excellent device performance in terms of steep subthreshold slope (80mV/dec) and on/off current ration higher than 108 is obtained for P-channel operation.